Electronic devices have become an integral part of daily life as never before. Systems such as personal computers and mobile phones have fundamentally reshaped how we work, how we play, and how we communicate. Each passing year brings the introduction of new devices such as digital music players, e-book readers and tablets, as well as improvements to preexisting families of products. These new devices show ever increasing innovation that continues to transform how we conduct our lives.
The rising importance of electronic systems to the world economy and modem culture has, to date, been enabled in significant part by the semiconductor industry's adherence to Moore's Law. Named after Gordon Moore, a founder of Intel who first observed the phenomenon, Moore's Law provides that the number of transistors that can be made inexpensively within the same area on an integrated circuit (or chip) steadily increases over time. Some industry experts quantify the law, stating, for example, that the number of transistors within the same area roughly doubles approximately every two years. Without the increase in functionality and related decreases in cost and size provided by Moore's Law, many electronics systems that are widely available today would not have been practicable or affordable.
For some time the semiconductor industry has succeeded in holding to Moore's Law by using bulk CMOS technology to make circuits in chips. Bulk CMOS technology has proven to be particularly “scalable,” meaning that bulk CMOS transistors can be made smaller and smaller while optimizing and reusing existing manufacturing processes and equipment in order to maintain acceptable production costs. Historically, as the size of a bulk CMOS transistor decreased, so did its power consumption, helping the industry provide increased transistor density at a reduced cost in keeping with Moore's Law. Thus, the semiconductor industry has been able to scale the power consumption of bulk CMOS transistors with their size, reducing the cost of operating transistors and the systems in which they reside.
In recent years, however, decreasing the power consumption of bulk CMOS transistors while reducing their size has become increasingly more difficult. Transistor power consumption directly affects chip power consumption, which, in turn, affects the cost of operating a system and, in some cases, the utility of the system. For example, if the number of transistors in the same chip area doubles while the power consumption per transistor remains the same or increases, the power consumption of the chip will more than double. This is due in part by the need to cool the resulting chip, which also requires more energy. As a result, this would more than double the energy costs charged to the end user for operating the chip. Such increased power consumption could also significantly reduce the usefulness of consumer electronics, for example, by reducing the battery life of mobile devices. It could also have other effects such as increasing heat generation and the need for heat dissipation, potentially decreasing reliability of the system, and negatively impacting the environment.
There has arisen among semiconductor engineers a widespread perception that continued reduction of power consumption of bulk CMOS is infeasible, in part because it is believed that the operating voltage VDD of the transistor can no longer be reduced as transistor size decreases. A CMOS transistor is either on or off. The CMOS transistor's state is determined by the value of a voltage applied to the gate of the transistor relative to a threshold voltage VT of the transistor. While a transistor is switched on, it consumes dynamic power, which can be expressed by the equation:Pdynamic=CVDD2f 
Where VDD is the operating voltage supplied to the transistor, C is the load capacitance of the transistor when it is switched on, and f is the frequency at which the transistor is operated. While a transistor is switched off, it consumes static power, which can be expressed by the equation: Pstatic=IOFF VDD, where IOFF is the leakage current when the transistor is switched off. Historically, the industry has reduced transistor power consumption primarily by reducing the operating voltage VDD, which reduces both dynamic and static power.
The ability to reduce the operating voltage VDD, depends in part on being able to accurately set the threshold voltage VT, but that has become increasingly difficult as transistor dimensions decrease because of a variety of factors, including, for example, Random Dopant Fluctuation (RDF). For transistors made using bulk CMOS processes, the primary parameter that sets the threshold voltage VT is the amount of dopants in the channel. Other factors that affect VT are halo implantation, source and drain extension, and other factors. In theory, this can be done precisely, such that the same transistors on the same chip will have the same VT, but in reality the threshold voltages can vary significantly. This means that these transistors will not all switch on at the same time in response to the same gate voltage, and some may never switch on. For transistors having a channel length of 100 nm or less, RDF is a major determinant of variations in VT, typically referred to as sigma VT or sigma VT, and the amount of sigma VT caused by RDF only increases as channel length decreases. As shown in FIG. 1, which is based on information provided by Intel Corporation, estimated experimental data, together with a keynote presentation by Kiyoo Itoh, Hitachi Ltd., IEEE International Solid-State Circuits Conference, 2009, the conventional wisdom among semiconductor engineers has been that increasing sigma VT in nanoscale bulk CMOS sets 1.0 V as a practical lower limit for the operating voltage VDD going forward. VDD is illustrated as a downward sloping function, with an industry goal to reduce to a TARGET area. The curve for sigma VT, however, increases with decreasing device feature size, where the RDF actually causes Vmin to increase. The power function of dynamic and static power is Power=CVDD2f+IVDD. Thus, overall power increases.
For these and other reasons, engineers in the semiconductor industry widely believe that bulk CMOS must be abandoned in future process nodes despite the fact that there are many known techniques for reducing sigma VT in short channel devices. For example, one conventional approach to reducing sigma VT in bulk CMOS involves acting to provide a non-uniform doping profile that increases dopant concentration in a channel as it extends vertically downward (away from the gate toward the substrate). Although this type of retrograde doping profile does reduce the sensitivity to the doping variations, it increases the sensitivity to short channel effects that adversely affect device operation. Because of short channel effects, these doping parameters are generally not scalable for nanoscale devices, making this approach not generally suitable for use with nanoscale, short channel transistors. With technology moving toward short channel devices formed at the 45 nm or even 22 nm process nodes, benefits of the retrograde approach in such devices are perceived to be limited.
Semiconductor engineers working to overcome these technological obstacles have also attempted to use super steep retrograde wells (SSRW) to address performance issues associated with scaling down to the nanoscale region. Like retrograde doping for nanometer scale devices, the SSRW technique uses a special doping profile, forming a heavily doped layer beneath a lightly doped channel. The SSRW profile differs from retrograde doping in having a very steep increase in dopant levels to reduce the channel doping to as low a level as possible. Such steep dopant profiles can result in reduction of short channel effects, increased mobility in the channel region, and less parasitic capacitance. However, it is very difficult to achieve these structures when manufacturing these devices for high volume, nanoscale integrated circuit applications. This difficulty is due in part to out-diffusion of the retrograde well and SSRW dopant species into the channel region, especially for a p-well device such as the NMOS transistor. Also, use of SSRW does not eliminate issues with random dopant density fluctuations that can increase sigma VT to unacceptable levels.
In addition to these and other attempts to work through shortcomings of existing bulk CMOS implementations, the industry has become heavily focused on CMOS transistor structures that have no dopants in the channel. Such transistor structures include, for example, fully depleted Silicon On Insulator (SOI) and various FINFET, or omega gate devices. SOI devices typically have transistors defined on a thin top silicon layer that is separated from a silicon substrate by a thin insulating layer of glass or silicon dioxide, known as a Buried Oxide (BOX) layer. FINFET devices use multiple gates to control the electrical field in a silicon channel. Such can have reduced sigma VT by having low dopants in the silicon channel. This makes atomic level variations in number or position of dopant atoms implanted in the channel inconsequential. However, both types of devices require wafers and related processing that are more complex and expensive than those used in bulk CMOS.
Given the substantial costs and risks associated with transitioning to a new technology, manufacturers of semiconductors and electronic systems have long sought a way to extend the use of bulk CMOS. Those efforts have so far proven unsuccessful. The continued reduction of power consumption in bulk CMOS has increasingly become viewed in the semiconductor industry as an insurmountable problem.